Alif Semiconductor /AE722F80F55D5LS_CM55_HE_View /NPU_HE /NPUHE_AXI_LIMIT0

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Interpret as NPUHE_AXI_LIMIT0

MAX_BEATS=Val_0x0, MEMTYPE=Val_0x0

Description

AXI Limit Register 0

Fields

MAX_BEATS	Burst split alignment 0 (Val_0x0): 64 bytes 1 (Val_0x1): 128 bytes 2 (Val_0x2): 256 bytes
MEMTYPE	Memory type 0 (Val_0x0): Device Non-Bufferable 1 (Val_0x1): Device Bufferable 2 (Val_0x2): Normal, Non-Cacheable, Non-Bufferable 3 (Val_0x3): Normal, Non-Cacheable, Bufferable 4 (Val_0x4): Write Through, No Allocate 5 (Val_0x5): Write Through, Read Allocate 6 (Val_0x6): Write Through, Write Allocate 7 (Val_0x7): Write Through, Read and Write Allocate 8 (Val_0x8): Write Back, No Allocate 9 (Val_0x9): Write Back, Read Allocate 10 (Val_0xA): Write Back, Write Allocate 11 (Val_0xB): Write Back, Read and Write Allocate
MAX_OUTSTANDING_READ_M1	Maximum number of [outstanding AXI read transactions - 1] in range 0 to 31
MAX_OUTSTANDING_WRITE_M1	Maximum number of [outstanding AXI write transactions - 1] in range 0 to 15

Links

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